Memory devices are susceptible to errors such as transient (or soft) errors. If these errors are not handled properly, they can cause a computing system to malfunction. Redundant information in the form of error correcting codes (ECCs) can be used to improve overall system reliability. The redundant information, however, increases the storage requirement of the memory system and, thereby, increases the cost of the memory system. Thus, ECC is typically only used on high-end or mission critical systems. Lower cost (or less critical) systems do not use ECC and provide a level of reliability which is appropriate to their usage.
In some cases, the extra bits of storage are added to the system by adding additional memory devices (e.g., dynamic random access memory (DRAM) devices). For example, a system using eight DRAMs to store data may also use an additional DRAM to store the check codes. In other cases, the extra bits are stored in a variant DRAM designed especially for use in ECC systems. For example, a non-ECC DRAM may have 256 Mbits of capacity and 16 outputs. The ECC variant of that DRAM may have 288 Mbits of capacity and 18 outputs. In both of these examples, the ECC systems have 12.5% more storage capacity than the non-ECC counterparts.
The use of different DRAM devices in ECC systems has a number of disadvantages. For example, there is an increase in costs associated with designing, manufacturing, and inventorying, two (or more) variants of a DRAM device. In addition, an ECC variant DRAM device is larger than its non-ECC counterpart and, therefore, more difficult to manufacture. Adding the extra bits to the ECC variant DRAM lowers the yield of devices and, thus, increases the cost of the devices. Another disadvantage of using two (or more) variants of a DRAM device is that memory controllers that interface with the DRAM devices are required to support additional pins (e.g., ECC pins). Also, an ECC variant DRAM module uses more space on a motherboard because its connector is larger than its non-ECC counterpart.
Each memory cell in a DRAM is constructed from a single transistor and a single capacitor and is called dynamic because its data decays and becomes invalid due to various leakage current paths to surrounding cells and to the substrate. To keep the data in the cells valid, each memory cell is periodically refreshed. Data in the DRAM cell array is refreshed every time it is read out of the cell array into the sense amplifiers and subsequently rewritten into the cell.
The memory controller is responsible for periodically performing refresh maintenance operations on the memory cell array. Every row of the memory array needs to be refreshed before the data in the row decays to an invalid state. In a low power mode, the DRAM is placed in a self-refresh state where the DRAM is responsible for performing the refreshes. As DRAM densities increase over time, the trend is to have more rows of memory, which in turn will increase the refresh overhead and refresh power.